In recent years, a standard using a spread spectrum clock (SSC) which spreads the spectrum of a reference clock signal to generate a spread spectrum clock signal has come into widespread use as measures for electro-magnetic compatibility (ENC) in, for example, a bus of a computer. For example, a down-spread mode is used as the spread mode in Universal Serial Bus (USE) 3.0 which is one of the serial bus standards for connecting a peripheral device to an information device such as a computer. In addition, for example, in PCI Express 3.0 (Gen3) which is an I/O serial interface, a center-spread mode is used as the spread mode.
However, there is no standard that uses an upper-spread mode as the spread mode. The reason is as follows. In the down-spread mode and the center-spread mode, an average bit rate does not exceed a standard value. However, in the upper-spread mode, peak and average bit rates are high and the operation margin of a device is reduced. In order to solve the problem, the device needs to be configured so as to correspond to a high bit rate and the operation margin of the device needs to increase. However, in this case, there is a disadvantage that a high technique is required or costs increase. For this reason, the upper-spread mode is hardly used.
However, in recent years, various types of digital communication devices have required high transmission capability, with an increase in the number of users or the spreading of multimedia communication. A bit error rate (hereinafter, simply referred to as an error rate) that is defined as the comparison between the number of times a code error occurs in received data and the total amount of received data has been known as one of the indexes for evaluating the quality of digital signals in these digital communication devices.
In a case in which a desired digital communication device is used as an object to be measured and the error rate of the object to be measured is measured, for example, a bit error rate measurement device disclosed in the following Patent Document 1 is used. In this type of bit error rate measurement device, in order to measure the allowable electrical stress range of the object be measured, a pattern generator applies an electrical stress signal with a known pattern as a test signal, the test signal is looped back inside or outside the object to be measured, and the loop-back signal is compared with the test signal received by the error detector to perform jitter tolerance measurement for measuring whether an error occurs according to the amount of stress applied.
However, in this type of bit error rate measurement device, in a case in which a margin test is performed for the object to be measured, a spread spectrum clock signal or a data signal needs to be generated and input to the object to be measured. Therefore, a pattern generator or a spread spectrum clock generator that can generate a spread spectrum clock signal in all of the upper-spread mode, the down-spread mode, and the center-spread mode is required.